1. Field of the Invention
The present invention relates to digital memories, and more particularly, to an address transition detection circuit for use in a digital memory.
2. Description of the Related Art
Address transition detection (ATD) circuits are commonly used in high speed digital memories. An ATD circuit detects whether there has been a transition made on its associated address line and generates a signal indicating the change. Because such a transition normally indicates that the user is accessing the memory to either read or write data, the detection of the transition can be used by a memory to signal the start of a sequence. In a read operation this results in new data being provided on the memory's output lines. The sequence can be partitioned into time segments so that the appropriate circuits are turned on at the appropriate times. This can keep the maximum peak currents under control which can help to reduce noise.
The use of ATD circuits can improve the speed and reduce the power consumption of a memory. Specifically, certain nodes can be pre-conditioned in response to the detected address line transitions. Such pre-conditioning improves the response time of the nodes. Furthermore, detecting address line transitions can be used to initiate the sequencing of the usage of power among the actual circuits which are used to provide the new data.
There are several factors which should be taken into consideration when designing an ATD circuit. Specifically, the circuit should be able to detect a transition on the address lines very quickly, especially in read operations where speed is often critical. A delay in the detection causes an increase in the access time which is contrary to the intended function of the circuit. Once a transition has been detected, the circuit generates a pulse which indicates to other circuitry that the respective address line has experienced a transition. The width of this pulse is normally carefully designed and controlled so that the duration of the pulse does not slow the access time.
The subject invention is best illustrated by first describing some aspects of a conventional memory system. FIG. 1 shows an exemplary conventional memory system 13. The core of the system is an Array 15 of memory cells, in this case flash memory cells, arranged in rows and columns with there being a total of 256K of eight bit words (one byte) in the Array. The individual cells (not depicted) are addressed by eighteen bits or address A0-A17, with nine bits being used by an X Decoder 17 to select the row of the Array 15 in which the target cell is located and the remaining nine bits being used by a Y decoder 19 to select the appropriate column of the Array 15.
Memory system 13 is of the type which contains an internal State Machine 21 to control the detailed operations of the memory system 13 such as the various individual steps necessary for carrying out programming, reading and erasing operations. The State Machine 21 thus functions to reduce the overhead required of the processor (not depicted) typically used in association with the memory system 13. Since programming and erasing operations for flash memories are relatively slow, these devices are considered to be "read mostly" memories where read access times determine the overall memory performance.
The address inputs A0-A17 are first received by an address buffer/latch 23. FIG. 2 shows a conventional ATD circuit 10 which may be included in the address buffer/latch 23. FIG. 3 shows the address cell 11 which receives the first address input A0. The other address inputs A1, A2, up to A17 have their own associated address cells 22, 24 and 26, respectively, which are identical to address cell 11.
The address cell 11 has two outputs. Output AddATDp0 indicates a positive transition on address input A0, and output AddATDn0 indicates a negative transition on address input A0. Some conventional address cells, however, have a single output which is activated whether the address transition is positive or negative. Furthermore, address cell 11 includes first and second one shot generators 12 and 14. Address input A0 is connected to the input of a TTL buffer 16, the output of which is connected through an inverter 18 to the first one shot 12. The first and second one shots 12 and 14 are connected together by an inverter 20 so that the two one shots will trigger on opposite polarity transitions.
Referring to FIG. 4, as the address input A0 changes state 25 or 31, one of the two one shots 12 or 14 generates a pulse 27 or 29, respectively, referred to herein as an ATD pulse, signifying that activity. Specifically, the first one shot 12 generates the ATD pulse 27 at the AddATDp0 output when the address line A0 experiences a positive transition 25, and the second one shot 14 generates the ATD pulse 29 at the AddATDn0 output when the address line A0 experiences a negative transition 31. The width of the ATD pulse 27 generated by the first one shot 12 is determined by the delay caused by the inverters 34, 36 and 38. Similarly, the width of the ATD pulse 29 generated by the second one shot 14 is determined by the delay caused by the inverters 40, 42 and 44.
Because each of the address inputs A0-A17 has its own address cell, a change on all of the address inputs causes 18 ATD pulses to be generated. However, when a new address is sent to the memory system 13, it is common for all of the address inputs A0-A17 to not change at exactly the same time. This results in the 18 ATD pulses not being generated at exactly the same time. In order to start the read sequence which results in new data being provided on the memory's output lines, it is important to know when the first one of the address inputs A0-A17 has experienced a transition. This is accomplished by ORing all of the outputs of the address cells 11, 22, 24, and 26 together. Due to the number of the address inputs A0-A17 and the fact that each address cell 11, 22, 24, and 26 will send either one or two lines to the OR circuit, a distributed OR gate 28 is usually implemented. The OR gate 28 generates an output pulse ATDout which is used by the memory system 13 to start the above-mentioned sequence.
Assuming that only two address inputs A0 and A1 are present in the memory system 13, as is shown in FIG. 4, the output pulse ATDout goes high 33 when the ATD pulse 27 AddATDp0 goes high, and the output pulse ATDout goes low 35 when the ATD pulse 41 AddATDp1 goes low. Similarly, the output pulse ATDout goes high 37 when the ATD pulse 29 AddATDn0 goes high, and the output pulse ATDout goes low 39 when the ATD pulse 43 AddATDn1 goes low. In other words, the output pulse ATDout goes high in response to the first address input which experiences a transition, and the output pulse ATDout returns low in response to the last ATD pulse going low, i.e., after all address inputs have transitioned and stabilized. Thus, if there is any transition on any of the address lines, a pulse is generated on the output ATDout.
Ideally, the timing of the address line transitions will be such that each ATD pulse will overlap with at least one other ATD pulse. For example, as shown in FIG. 4, the ATD pulse 27 AddATDp0 overlaps with the ATD pulse 41 AddATDp1. If all of the ATD pulses overlap with at least one other ATD pulse, then a single continuous output pulse ATDout will be generated by the OR gate 28.
FIG. 2 shows that all of the AddATDp and AddATDn lines are routed to the OR gate 28. This means that in the memory system 13, which has 18 address lines, 36 lines would have to be sent to the OR gate 28. This scenario has the disadvantage of causing a significant amount of bussing and silicon usage. Furthermore, many of the AddATDp and AddATDn lines would be running long distances to the OR gate 28, and as such, the drivers of the AddATDp and AddATDn signals would need to be sized up which would either have an adverse effect on the die space or speed. One way to reduce the number of lines that are routed is to OR the AddATDp and AddATDn outputs inside each of the address cells 11, 22, 24, and 26 and then route only one line for each circuit to the OR gate 28. However, this scenario has the disadvantage of causing another one or two delay states in the path of these signals. Any additional delay in the AddATDp and AddATDn outputs also delays the generation of the output pulse ATDout which should be extremely responsive and fast.
An alternative implementation of the circuit shown in FIG. 2 is to route line 30 of the OR gate 28 to each of the address cells 11, 22, 24, and 26, rather than sending the AddATDp and AddATDn lines to the OR gate 28. Thus, rather than having the AddATDp and AddATDn lines travel, the line 30 travels. In this scenario the OR gate 28 is distributed across all of the address cells 11, 22, 24, and 26. Because only the one line 30 is routed, the real estate penalty is minimized. The drawback, however, is managing the OR gate 28 structure and its associated load 32. As shown in FIG. 2, a load circuit 32 is associated with the OR gate 28 in this approach. Due to the number of address lines, there is a large capacitive load on line 30. Because of this large capacitance, the load 32 must be large enough (i.e., have a small impedance) to pull line 30 up once the AddATDp and AddATDn signals have been deasserted. Otherwise, the output pulse ATDout will be deasserted slowly, as shown at 35 and 39 in FIG. 4. However, if the load 32 is large, it is difficult to pull line 30 down during AddATDp and AddATDn assertion. This causes the output pulse ATDout to be asserted slowly, as shown at 33 and 37 in FIG. 4. In order to speed up the pull down of line 30, the AddATDp and AddATDn pull downs can be beefed up; however, this also creates additional speed problems by increasing the capacitance loading on the outputs of the AddATDp and AddATDn drivers.
Thus, there is a need for an ATD circuit in which the number of lines which are routed across the die is minimized in order to conserve die real estate. Furthermore, there is a need for an ATD circuit having an output pulse which is asserted as fast as possible in response to an address line transition, and which is deasserted as fast as possible after all address lines have transitioned and stabilized.